In computer systems and the like, informational signals, normally in pulse form, are transmitted along data signal paths from one section of the system to another, for instance from the central processor unit (CPU) to a tape handler. It has become popular to provide a bus device as the common bidirectional data signal path for such systems and more recently such buses have been tri state buses. A tri state bus is a bus whose lines can be driven low, high or not at all (high impedance state). When data signals are being transferred via a tri state bus, current is driven along the bus by the unit sending the data, and pulled from the bus by the unit receiving the data. The reverse is true when the receiving unit, mentioned above, becomes the sending unit and when the sending unit, above, becomes the receiving unit. Normally the sending units and receiving units are turned on, or activated, by enable signals from a clock generator (normally sent through some control circuitry). Heretofore, a single set of enable signals has been used (in conjunction with certain control signals) to turn units on. In the prior art such enable signals have been individually generated and therefore, not overlapping. Nonetheless, it has been found that under certain circumstances, a unit which is driving current in a first direction has a certain amount of current flow inertia so that after the enable signal has terminated, the unit continues to drive current thereby overlapping the time period of a subsequent enable signal. Under such circumstances, since a second unit has been enabled to drive current in a second direction, many undesirable effects occur because of the signal currents being driven in two directions simultaneously.